1. Field of the Invention
The present invention relates to a PLL circuit used in a digital device such as an optical transmission device or a mobile communications device.
2. Description of the Related Art
A PLL circuit is heretofore known, which generates and outputs, based on a predetermined clock originating from an input clock, an output clock of a frequency N times (where N is a positive integer including 1) higher than that of the predetermined clock. This PLL circuit is a circuit, which is favorably incorporated into a digital device such as an optical transmission device or a mobile communications device, and which generates a basic clock required for the digital device.
The purpose of having a PLL circuit in a digital device is to convert a frequency of a clock, which is inputted to the PLL circuit, into a frequency required for the digital device. In addition, a PLL circuit is also used for the purpose of suppressing noise which is superimposed on a clock to be an input. Moreover, even in a state where a clock is not inputted to the PLL circuit, in a digital device, the PLL circuit is also used as a circuit for supplying a clock to a digital circuit which requires a clock to be continuously supplied thereto. This is because the PLL circuit generates a clock of a predetermined frequency without discontinuing a generation of an output clock.
FIG. 5 is a diagram showing a configuration of a conventional PLL circuit using an active filter.
A PLL circuit 100 shown in FIG. 5 is provided with a frequency divider 101. The frequency divider 101 generates a first clock CLK1 by dividing an input clock CLKIN by M (where M is a positive integer not less than 1).
In addition, the PLL circuit 100 is provided with a phase comparator 102 to which the first clock CLK1 and a third clock CLK3 to be described later are inputted. This phase comparator 102 compares a phase of the first clock CLK1 with that of the third clock CLK3. Then, the phase comparator 102 outputs a phase comparison result signal POUT corresponding to a phase difference between these first and third clocks CLK1 and CLK3.
Moreover, the PLL circuit 100 is provided with a pre-filter 103, an active filter 104 and a post-filter 105. The pre-filter 103 is configured of a resistive element 103a and a capacitor element 103b. The active filter 104 is configured of a resistive element 104a, an operational amplifier 104b, a resistive element 104c, a capacitor element 104d and a power supply section 104e. The resistive element 104c and the capacitor element 104d are connected between an input and an output of the operational amplifier 104b, and form an integration circuit. The power supply section 104e generates a reference voltage. Furthermore, the post-filter 105 is configured of a resistive element 105a and a capacitor element 105b. It should be noted that the pre-filter 103 and the post-filter 105 are provided for the purpose of removing a signal of a further higher frequency component than a signal of a high frequency component to be removed by the active filter 104, in the phase comparison result signal POUT to be outputted from the phase comparator 102.
Furthermore, the PLL circuit 100 is provided with a voltage controlled type oscillator 106. This voltage controlled type oscillator 106 outputs a second clock CLK2 of a frequency N times (where N is a positive integer including 1) higher than that of the first clock CLK1, upon receipt of a control input signal CNT to be described later. The second clock CLK2 is outputted to the outside thereof as an output clock CLKOUT via a buffer 107 while being inputted to a frequency divider 108 as well.
The frequency divider 108 outputs the third clock CLK3 by dividing a frequency of the second clock CLK2 by N. The third clock CLK3 is inputted to the phase comparator 102.
In the PLL circuit 100 configured in the manner described above, a phase comparison result signal POUT corresponding to the phase difference between the first CLK1 and the third CLK3 is outputted from the phase comparator 102. The phase comparison result signal POUT is then inputted to one end of the operational amplifier 104b via the pre-filter 103. The operational amplifier 104b obtains a voltage by causing the integration circuit to integrate an output voltage from the operational amplifier 104b and to feed back the result of the integration operation, the integration circuit being configured of the resistive element 104c and the capacitor element 104b. The operation amplifier 104b extracts a low frequency component of the phase comparison result signal POUT by comparing the obtained voltage with the reference voltage inputted to the other end of the operational amplifier 104b. Then, the operation amplifier 104b inputs the low frequency component of the phase comparison result signal POUT, as a control input signal CNT, to the voltage controlled type oscillator 106 via the post-filter 105. As described above, in the PLL circuit 100, the phase comparison result signal POUT, which is a phase error signal corresponding to the difference between the first clock CLK1 and the third clock CLK3, is reflected in a control input signal CNT of a level of a direct current, which is inputted to the voltage controlled type oscillator 106. By this reflection, a loop operation is performed so that the phases of the first clock CLK1 and the third clock CLK3 can be matched with each other. By this loop operation, the output clock CLKOUT to be outputted from the PLL circuit 100 can be synchronized in phase with the input clock CLKIN, and thus an output frequency defined by the following relationship can be obtained.(Frequency of Output Clock CLKOUT)=(Frequency of Input Clock CLKIN)×N/M
FIG. 6 is a diagram showing a configuration of a conventional PLL circuit using a passive filter.
A PLL circuit 200 shown in FIG. 6 is different from the PLL circuit 100 shown in FIG. 5 in that the pre-filter 103 and the active filter 104 are replaced with a lag-lead filter 201.
The lag-lead filter 201 is a low-pass filter constituted of a resistive element 201a, a resistive element 201b and a capacitor element 201c. One end of the resistive element 201a is connected to an output of the phase comparator 102. The resistive element 201b and the capacitor element 201c are connected in series between the other end of the resistive element 201a and the ground.
In this PLL circuit 200, the phase comparison result signal POUT, which corresponds to a phase difference between the first clock CLK1 and the third clock CLK3,and which is outputted from the phase comparator 102, is inputted to the lag-lead filter 201. Subsequently, a low frequency component of the phase comparison result signal POUT is extracted by the lag-lead filter 201. The extracted low frequency component is inputted as a control input signal CNT to the voltage controlled type oscillator 106 via the post-filter 105. As described above, in this PLL circuit 200 as well, the phase comparison result signal POUT, which is a phase error signal corresponding to the phase difference between the first clock CLK1 and the third clock CLK3, is reflected in the control input signal CNT to be inputted to the voltage controlled type oscillator 106. By the reflection, a loop operation is performed so that the phases of the first clock CLK1 and the third CLK3 can be matched with each other. By this loop operation, the output clock CLKOUT outputted from the PLL circuit 200 can be synchronized in phase with the input clock CLKIN.
In general, in a PLL circuit, a period from the time when an input clock is inputted, to the time when an output clock is synchronized in phase with the input clock is termed as a pull-in time, and is considered as one of performances of the PLL. This pull-in time is largely dependent on a loop band (cutoff frequency) and a damping factor, which are main performances of the PLL. Accordingly, in order to shorten the pull-in time, it is necessary to increase the loop band or to decrease the damping factor. To this end, in the pull-in process, arrangement for the loop band to increase and for the damping factor to decrease is made, and thus the pull-in time is shortened.
Here, in Japanese Patent Application Laid-open Official Gazette No. 10-308667, proposed is a technique for shortening a pull-in time in a PLL circuit in which an intermittent operation is employed for the purpose of reducing power consumption. This technique makes it possible to shorten a pull-in time even in a case where a large difference between the phases of an input clock and an output clock is present when returning to a PLL operation. In this technique, reset functions are respectively provided for both a static frequency divider which divides a frequency of the input clock, and a variable frequency divider which divides a frequency of the output clock. At the point when the PLL circuit returns to the PLL operation, an initial phase difference is detected by comparing the phases of the corresponding signals respectively from the two frequency dividers. Then, one of the frequency dividers, in which the signal is advanced in phase, is reset. Subsequently, by releasing the reset in conjunction with the start of the outputting of the frequency divider, in which the signal is delayed in phase, the matching of the phases is performed.
In the technique proposed in Japanese Patent Application Laid-open Official Gazette No. 10-308667, however, the signals, which are inputted to the phase comparator respectively from the two frequency dividers, are transmitted to the subsequent stage after approximately matching the phases of the signals with each other. Accordingly, although the pull-in time after transmitting the signals to the subsequent stage can be shortened, the transmission of the signals to the subsequent stage is blocked until the phases are approximately matched with each other. For this reason, there is a problem that it takes time to complete the pull-in operation when viewed from the time when the input clock is restarted. Moreover, there is a possibility that the phases may change when switching from a period for which to detect the initial phase difference to a period after the matching of the phases is performed.